Instruction Level Parallelism

コンピュータサイエンスのシステム構成のひとつの課題は命令の順番を決める方法です。
An important topic for the past 25 years has been instruction level parallelism, which seems to be the ability for multiple instructions to be executed on one or more processors simultaneously. The capability of parallelism has made the subject of instruction scheduling an important topic. By scheduling, it seems that what is meant is the determination of the order in which instructions output by a compiler are executed in and the hardware upon which they are executed. Two types of scheduling are hardware scheduling and software scheduling. These also seem to be known as dynamic and static.
Hardware scheduling seems to involve facilities like crossbars, microcode-controlled devices, and rotating registers (Itanium). I am not certain about how such devices enable multiple instructions to run simultaneously, but I suspect they enable data to be moved between stages of a single pipeline (such as arithmetic and argument fetch).
Software scheduling seems to be divided into trace scheduling and software pipelining. Trace scheduling involves unrolling of loops and branch prediction. Software pipelining also involves manipulating code by moving instructions which were in separate loop iterations into a single iteration. Thus, I am not sure how these are alternate strategies.